Typical processes for fabrication of MOSFETs require that numerous steps be performed. A silicon substrate must have silicon dioxide SiO.sub.2 grown upon its surface. The oxide must then be etched to open source and drain regions through which dopants are entered and driven in via high temperature diffusions. Next, further oxide etches must be performed to remove all but the gate and gate pad oxide, then a layer of metal, which is typically aluminum must be deposited and etched. An additional sinter anneal is normally performed to cause good electrical contact between the metal and the underlying silicon.
Methods which reduce the number of steps, or the complexity of fabrication,or the energy required to fabricate MOSFETs are always of interest. A method for fabrication of MOSFETs which could reduce the number of steps required to the growing of, and etching of silicon dioxide, the deposition of a metal, and the annealing of the result, would be of great utility.
In 1974 a thesis titled "DESIGN AND FABRICATION OF SUB-MICRON CHANNEL MOS. TRANSISTORS BY DOUBLE ION IMPLANTATION" was submitted by James D. Welch to the Electrical Engineering Department of Toronto University. Disclosed in that work was the procedure Mr. Welch developed for fabricating MOSFET devices via the implantation of Boron ions around deposited and etched chromium patterns atop of N type silicon upon which had been grown 1000.ANG. of SiO.sub.2. During his work, Mr. Welch investigated an MOS capacitor to determine how chromium interacts with SiO.sub.2 during an anneal at 650.degree. C. That temperature was of particular significance in the fabrication procedure. While investigating the MOS capacitor Mr. Welch discovered that chromium deposited on the back, unpolished side of the silicon substrate, when annealed at 650.degree. C. formed a very good rectifying junction. Recently Mr. Welch had a computer search run for authority on the use of chromium and silicon as a system. No patents were discovered but two articles were turned up. The articles, "COMPOUND FORMATION BETWEEN SILICON AND CHROMIUM" by Yacobi, Szadkowski and Zukotynski, J. App. Phys., Dec., 1980; and "METALLURGICAL AND ELECTRICAL PROPERTIES OF CHROMIUM SILICON INTERFACES", by Martinez and Esteve, Solid State Electronics, 1980; document that the effect which Mr. Welch noted in his earlier work exists and is due to the formation of chromium disilicide CrSi.sub. 2. It is the benefit afforded by the diode junctions formed from CrSi.sub.2, in conjunction with a facilitating device geometry, which the present method utilizes to produce MOSFETs in an economical and simple way. The minimal number of steps in the process also provides for enhanced yield of devices per substrate processed.